1. Field of the Invention
The present invention relates to a two-dimensional inverse discrete cosine transformation circuit for use in an MPEG2 (Moving Picture Export Group Phase 2) video decoder.
2. Description of the Related Art
Conventional two-dimensional inverse discrete cosine transformation circuits for use in an MPEG video decoder execute two-dimensional inverse discrete cosine transformation by conducting first one-dimensional inverse discrete cosine transformation with respect to 64 data as a unit (block) and subsequently conducting second one-dimensional inverse discrete cosine transformation with the data of the same block. One of conventional two-dimensional inverse discrete cosine transformation circuits of this kind is disclosed, for example, in the literature "A Single-Chip MPEG1 Audio/Video Decoder" (Y. Katayama, et. al). Structure of the conventional two-dimensional inverse discrete cosine transformation circuit disclosed in the literature is shown in FIG. 9.
As shown in the figure, the conventional two-dimensional inverse discrete cosine transformation circuit includes serial-parallel conversion circuits 11 and 16 for conducting 1:8 serial-parallel conversion with respect to input data and outputting converted data, an input switching circuit 12 for receiving input of the outputs of the serial-parallel conversion circuits 11 and 16 and selectively outputting either of them, a one-dimensional inverse discrete cosine transformation circuit 13 for receiving input of the output of the input switching circuit 12 to conduct one-dimensional inverse discrete cosine transformation, a serial-parallel conversion circuit 14 for receiving input of the output of the one-dimensional inverse discrete cosine transformation circuit 13 to conduct 2:1 serial-parallel conversion, and a memory 15 for receiving input of the output of the serial-parallel conversion circuit 14 and temporarily storing and then outputting the same to the serial-parallel conversion circuit 16.
One-dimensional inverse discrete cosine transformation here is transformation expressed by the following equation (1). EQU f(x)=.tau.c(u)F(u)cos{(2x+1)u.pi./16}/2 (1)
In the above expression, x and u represent an integer value of 0 to 7, and C(u) attains 1/.sqroot.2 when u=0 and attains 1 when u=1, . . . , 7. .SIGMA. represents a sum of u=0, . . . , 7, while .pi. represents a circle ratio. According to this expression, eight data after transformation will be calculated from eight data.
In thus structured conventional two-dimensional inverse discrete cosine transformation circuit, when one data is input at each clock to the serial-parallel conversion circuit 11 through an input pin, the circuit 11 conducts 1:8 serial-parallel conversion with respect to accumulated eight data eight clocks after. Then, the output of the serial-parallel conversion circuit 11 is applied to the one-dimensional inverse discrete cosine transformation circuit 13 via the input switching circuit 12, whereby the one-dimensional inverse discrete cosine transformation circuit 13 conducts the above-described one-dimensional inverse discrete cosine transformation with respect to the applied eight data as one group. The output data of the one-dimensional inverse discrete cosine transformation circuit 13 is serial-parallel-converted by the serial-parallel conversion circuit 14 and stored in memory 15. The memory 15 sequentially stores data row by row at 64 addresses of eight rows by eight columns, for example.
When data of one block, that is, 64 data is written at the memory 15, the input switching circuit 12 switches input to the one-dimensional inverse discrete cosine transformation circuit 13 from the serial-parallel conversion circuit 11 to the serial-parallel conversion circuit 16. As a result, the data written at the memory 15 is recursively input to the one-dimensional inverse discrete cosine transformation circuit 13 through the serial-parallel conversion circuit 16.
The serial-parallel conversion circuit 16 sequentially reads data on the basis of a column of the addresses of the memory 15 to conduct 1:8 serial-parallel conversion. The data again subjected to serial-parallel conversion is applied to the one-dimensional inverse discrete cosine transformation circuit 13 via the input switching circuit 12, so that the one-dimensional inverse discrete cosine transformation circuit 13 conducts one-dimensional inverse discrete cosine transformation in the same manner as in the first transformation. The output data thus subjected to the one-dimensional inverse discrete cosine transformation twice is output through the serial-parallel conversion circuit 14 as output data of the two-dimensional inverse discrete cosine transformation circuit.
By thus repeating one-dimensional inverse discrete cosine transformation twice, two-dimensional inverse discrete cosine transformation is conducted. Two-dimensional inverse discrete cosine transformation here is transformation expressed by the following equation (2). EQU f(x,y)=.SIGMA..SIGMA.'c(u)c(v)F(u)F(v)cos{(2x+1)u.pi./16} cos{(2y+1)v.pi./16} (2)
In the above expression, x, y, u and v represent an integer value of 0 to 7, and C(u) and C(v) attain 1/.sqroot.2 when u=0 and v=0 and attain 1 when u=1, . . . , 7 or v=1 . . . , 7. .SIGMA. represents a sum of u=0, . . . , 7 and Z' represents a sum of v=0, . . . , 7, while .pi. represents a circle ratio.
Operation of the conventional two-dimensional inverse discrete cosine transformation circuit will be described with reference to time charts of FIGS. 10 and 11.
In FIG. 10, when data input starts at TO, every time input of eight data is completed, the data is applied to the one-dimensional inverse discrete cosine transformation circuit 13 (FIG. 10, L0, L1, . . . ). At this time, since the one-dimensional inverse discrete cosine transformation circuit 13 is capable of processing two data at one clock, input to the one-dimensional inverse discrete cosine transformation circuit 13 only needs to be conducted at four clocks. At the remaining four clocks before eight subsequent input data is accumulated, the one-dimensional inverse discrete cosine transformation circuit 13 is at an input waiting state (FIG. 10, 100). Every time data is applied to the one-dimensional inverse discrete cosine transformation circuit 13 at timing L0, L1, . . . , data (FIG. 10, L'0, L'1, . . . ) is calculated whose first one-dimensional inverse discrete cosine transformation is completed after a period of an internal processing time (FIG. 10, 200) of the one-dimensional inverse discrete cosine transformation circuit 13.
At the completion of the foregoing processing conducted with respect to 64 input data (FIG. 11, T1), data to be applied to the one-dimensional inverse discrete cosine transformation circuit 13 is switched from the data as the output of the serial-parallel conversion circuit 11 to that as the output of the serial-parallel conversion circuit 16 (FIG. 11, 300) to apply eight data each read from the memory 15 to the one-dimensional inverse discrete cosine transformation circuit 13 (FIG. 11, M0) and calculate data subjected to second one-dimensional inverse discrete cosine transformation. At this time, no data input through the 20 input pin is possible during the execution of the second one-dimensional inverse discrete cosine transformation (FIG. 11, 400). Assuming a time from T0 of FIG. 10 to T1 of FIG. 11 to be represented as T, time required for processing data of one block, that is, 64 data, will be therefore represented as 2T.
In other words, the conventional inverse discrete cosine transformation circuits need to conduct first one-dimensional inverse discrete cosine transformation with respect to all the 64 data and then conduct second one-dimensional inverse discrete cosine transformation after switching input. During the execution of the second one-dimensional inverse discrete cosine transformation, no new data input is acceptable. As a result, much time is required for the processing of data of one block, that is, 64 data.
To reduce a time required for the above-described two-dimensional inverse discrete cosine transformation processing, proposed is a method of eliminating an input waiting state of a one-dimensional inverse discrete cosine transformation circuit to reduce data processing time for one block by half by inputting two data each at one clock. However, since in an MPEG video decoder, an inverse quantization circuit for conducting inverse quantization processing, which is pre-processing of two-dimensional inverse discrete cosine transformation processing, is structured to process one data at one clock because of conditions of circuit scale, this method is not desirable in view of a circuit scale of the entire MPEG2 video decoder.